1. Field of the Invention
The present invention relates to the word-by-word electrically reprogrammable nonvolatile memory having memory cells arranged in a matrix.
2. Description of the Prior Art
A floating gate memory cell or the construction of nonvolatile electrically reprogrammable memories is known from the IEEE Transactions on Electron Devices, Vol. ED-24, No. 5, May 1977, pp. 606-610, which is fully incorporated herein by this reference. In these field effect transistors, a floating memory gate, isolated on all sides, and a controllable control gate are arranged vertically above the channel segment, whereby the control gate covers the entire channel segment, whereas the floating gate covers only a portion of the channel segment. This so-called split gate structure avoids errors upon reading erased memory cells having a depletion character. The charging of the floating memory gate occurs by means of channel injection. To that end, electrons are accelerated in a short channel and fed to the memory gate by means of an additional electrical cross field. The discharging or erasing of the floating gate occurs by means of a back-tunneling of the electrons upon the application of a high electrical voltage between the control gate and a diffusion area.
In my U.S. patent application, Ser. No. 942,320, filed Sept. 14, 1978, corresponding to German patent application P 27 43 422.6, I disclose a word-by-word erasable nonvolatile memory constructed in floating gate technology. Both the charging and the discharging of the floating gate occurs by means of a direct transfer of electrons between the floating gate and the substrate, whereby a high electric field of suitable polarity is applied between the floating gate and the substrate.
A metal-nitride-oxide-semiconductor (MNOS) memory cell for the production of nonvolatile memories is known as an example for a holding memory from the publication Siemens Forschungs-and Entwicklungsberichte, Springer-Verlag, Vol. 4 (1974), No. 4, pp. 213-219. In this memory cell, a charge storage occurs by means of an electric transferring of traps on the interface between a nitride layer and an oxide layer. The charging and the discharging of the traps occurs by means of electron transfers through tunneling, given great electric field strength.
Memory cells which function in a manner similar to MNOS transistors are known from the publication IEEE Transactions on Electron Devices, Vol. ED-24, No. 5, May 1977, pp. 584-586, fully incorporated herein by this reference, in which, however, the layer sequence metallic gate electrode, nitride, oxide is replaced by means of transistors which have a layer sequence of polysilicon, oxynitride, nitride and oxide.
In all previously known memories which are constructed of the aforementioned memory cells, the erase or, respectively, programming time is permanently determined and adjusted by way of an external time element. The erase and programming times are to be selected so large that fluctuations of the erase and programming properties of the individual cells, caused for reasons of production technology, are taken into consideration not only within a chip, but also with respect to different fabrication batches. Moreover, the tolerance fluctuations of the time duration caused by means of the time element itself must also be taken into consideration. High programming and erasing times involve the danger of adjacent word interference and often also mean a deterioration of the programming memories, particularly in memory cells in which the write process occurs by means of channel injection. High write-erase times reduce the number of allowable write-erase cycles. In order to achieve minimum write-erase times and, therefore, to increase the life expectancy and the quality of corresponding semiconductor memories, it would be desirable to equip semiconductor memories in such a manner that an external time element is superfluous and to have only the fluctuations within one and the same chip have an influence in determining the write-erase duration, whereas fluctuations with respect to different semiconductor batches are not taken into consideration. By so doing, a significant reduction of the write-erase times can be achieved and the quality, as well as the life expectancy, of the memories concerned can be correspondingly increased.